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80C196EA CHMOS 16-BIT MICROCONTROLLER
Commercial
Preliminary Datasheet
Product Features
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40 MHz Operation Optional Clock Doubler 2 Mbytes of Linear Address Space 1 Kbyte of Register RAM 3 Kbytes of Code RAM Register-Register Architecture Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits 2 peripheral interrupt handlers (PIH) provide direct hardware handling of up to 16 peripheral interrupts Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines Up to 83 I/O port pins 2 full-duplex serial ports with dedicated baud-rate generators Enhanced synchronous serial unit 8 pulse-width modulator (PWM) outputs with 8-bit resolution 16-bit watchdog timer Sixteen 10-bit A/D channels with auto-scan mode and dedicated results registers
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Serial debug unit provides read and write access to code RAM with no CPU overhead Chip-select unit (CSU) 3 chip-select pins Dynamic demultiplexed/multiplexed address/data bus for each chip-select Programmable wait states (0, 1, 2, or 3) for each chip-select Programmable bus width (8- or 16-bit) for each chip-select Programmable address range for each chip-select Event processor array (EPA) 4 flexible 16-bit timer/counters 17 high-speed capture/compare channels 8 output-only channels capture value of any other timer upon compare, providing easy conversion between angle and time domains Programmable clock output signal 160-pin QFP package Complete system development support High-speed CHMOS technology
Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order No: 273153-001 January 1998
80C196EA - Commercial
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80C196EA - Commercial may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation PO Box 5937 Denver CO 80217-9808 call 1-800-548-4725 Copyright (c) Intel Corporation 7/8/97 *Third-party brands and names are the property of their respective owners.
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Preliminary Datasheet
80C196EA - Commercial
Contents
1.0 2.0 3.0 4.0 5.0 6.0
6.1 6.2 6.3 6.4 6.5 6.6 6.7
Product Overview....................................................................................................1 Nomenclature Overview ........................................................................................ 2 Pinout..........................................................................................................................3 Signals........................................................................................................................7 Address Map ..........................................................................................................10 Electrical Characteristics.....................................................................................11
DC Characteristics ........................................................................................ 11 AC Characteristics -- Multiplexed Bus Mode................................................ 13 AC Characteristics -- Demultiplexed Bus Mode ........................................... 17 Deferred Bus Timing Mode ........................................................................... 20 AC Characteristics -- Serial Port, Shift Register Mode................................. 21 AC Characteristics -- Synchronous Serial Port ............................................ 22 A/D Sample and Conversion Times .............................................................. 23 6.7.1 AC Characteristics -- A/D Converter, 10-bit Mode .......................... 24 6.7.2 AC Characteristics -- A/D Converter, 8-bit Mode ............................ 25 External Clock Drive...................................................................................... 26 Test Output Waveforms ................................................................................ 27
6.8 6.9
7.0
7.1
Thermal Characteristics ......................................................................................28
80C196EA Errata .......................................................................................... 28
8.0
DataSheet Revision History ...............................................................................28
Preliminary Datasheet
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80C196EA - Commercial
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 80C196EA Block Diagram ...............................................................................1 Product Nomenclature .....................................................................................2 S80C196EA 160-pin QFP Package .................................................................3 System Bus Timing Diagram (Multiplexed Bus Mode) ...................................15 READY Timing Diagram (Multiplexed Bus Mode)..........................................16 System Bus Timing Diagram (Demultiplexed Bus Mode) ..............................18 READY Timing Diagram (Demultiplexed Bus Mode) .....................................19 Deferred Bus Mode Timing Diagram..............................................................20 Serial Port Waveform -- Shift Register Mode ................................................21 Synchronous Serial Port ................................................................................22 External Clock Drive Waveforms ...................................................................26 AC Testing Output Waveforms ......................................................................27 Float Waveforms During 5.0 Volt Testing ......................................................27
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description of Product Nomenclature ..............................................................2 80C196EA 160-pin QFP Package Pin Assignments........................................4 Pin Assignment Arranged by Functional Categories........................................5 Signal Descriptions ..........................................................................................7 80C196EA Address Map................................................................................10 DC Characteristics at VCC = 4.5 V - 5.5 V.....................................................11 AC Characteristics, Multiplexed Bus Mode ....................................................13 AC Timing Symbol Definitions........................................................................14 AC Characteristics, Demultiplexed Bus Mode ...............................................17 Serial Port Timing -- Shift Register Mode .....................................................21 Synchronous Serial Port Timing.....................................................................22 10-bit A/D Operating Conditions ....................................................................24 10-bit Mode A/D Characteristics Over Specified Operating Conditions .........24 8-bit A/D Operating Conditions ......................................................................25 8-bit Mode A/D Characteristics Over Specified Operating Conditions ...........25 External Clock Drive.......................................................................................26 Thermal Characteristics .................................................................................28
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Preliminary Datasheet
80C196EA - Commercial
1.0
Product Overview
The 80C196EA are typically used for high speed event control systems. Commercial applications include modem, motor-control systems, printers, photocopiers, air-conditioner control systems, disk drives and medical instruments. It is especially well suited to applications that benefit from its processing speed and enhanced peripheral set.
Figure 1. 80C196EA Block Diagram
Port 11
Port 10
EPORT
Port 12
Watchdog Timer
Stack Overflow Module
A/D Converter
Pulse-width Modulators
SSIO0 SSIO1
Peripheral Addr Bus (10)
Peripheral Data Bus (16)
SIO0
Baud-rate Generator
Bus Control A20:16 A15:0 AD15:0
Memory Data Bus (16)
Memory Addr Bus (24)
Bus Controller
Chip-select Unit
Port 2
Peripheral Interrupt Handler Peripheral Transaction Server Interrupt Controller
SIO1
Baud-rate Generator
Bus-Control Interface Unit Queue Microcode Engine
Ports 7,8
17 Capture/ Compares EPA 4 Timers 8 Output/ Simulcaptures
Source (16) Port 9 Memory Interface Unit
ALU
Register RAM 1 Kbyte
Destination (16)
Code/Data RAM 3 Kbytes
Serial Debug Unit A4609-01
The 80C196EA is highly integrated with an enhanced peripheral set. The serial debug unit (SDU) provides system debug and development capabilities. The SDU can set a single hardware breakpoint and provides read and write access to code RAM through a high-speed, dedicated serial link. A stack overflow/underflow monitor assists in code development by causing an unmaskable interrupt if the stack pointer crosses a user-defined boundary. The 16-channel A/D converter supports an auto-scan mode that operates with no CPU overhead. Each A/D channel has a dedicated result register. The EPA supports high-speed input captures and output compares with 17 programmable, high-speed capture/compare channels. Eight output-only channels provide support for time-base conversions by capturing the value of one of four timers when a compare occurs.
Preliminary Datasheet
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80C196EA - Commercial
2.0
Nomenclature Overview
Figure 2. Product Nomenclature
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Table 1. Description of Product Nomenclature
Parameter Temperature and Burn-in Options Packaging Options Program Memory Options Process Information Product Family Device Speed S 0 C 196EA no mark 40 MHz Options Description Commercial operating temperature range (0 C to 70 C Ambient) with Intel standard burn-in. QFP CPU only - no internal ROM CHMOS
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A2815-01
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Preliminary Datasheet
80C196EA - Commercial
3.0
Pinout
Figure 3. S80C196EA 160-pin QFP Package
AD0 / P3.0 AD1 / P3.1 AD2 / P3.2 AD3 / P3.3 AD4 / P3.4 AD5 / P3.5 AD6 / P3.6 AD7 / P3.7 VCC VCC VSS VSS AD8 / P4.0 AD9 / P4.1 AD10 / P4.2 AD11 / P4.3 AD12 / P4.4 AD13 / P4.5 AD14 / P4.6 AD15 / P4.7 P5.7 / RPD P5.4/BREQ#/TMODE# P5.6 / READY P5.1 / INST P5.0 / ALE P5.5 / BHE# / WRH# P5.3 / RD# P5.2 / WR# / WRL# VSS VCC A20 / EPORT.4 A16 / EPORT.0 A17 / EPORT.1 A18 / EPORT.2 A19 / EPORT.3 EPORT.5 / CS0# EPORT.6 / CS1# EPORT.7 / CS2# NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A15 A14 A13 A12 A11 A10 A9 A8 VCC VSS A7 A6 A5 A4 A3 A2 A1 A0 P9.7 / OS7 P9.6 / OS6 P9.5 / OS5 P9.4 / OS4 P9.3 / OS3 P9.2 / OS2 P9.1 / OS1 P9.0 / OS0 P7.0 / EPA0 / T1CLK P7.1 / EPA1 / T1RST P7.2 / EPA2 / T2CLK P7.3 / EPA3 / T2RST P7.4 / EPA4 / T3CLK P7.5 / EPA5 / T3RST VSS VCC P7.6 / EPA6 / T4CLK P7.7 / EPA7 / T4RST P8.7 / EPA15 P8.6 / EPA14 P8.5 / EPA13 NC
S80C196EA
View of component as mounted on PC board
P8.4 / EPA12 P8.3 / EPA11 P8.2 / EPA10 P8.1 / EPA9 P8.0 / EPA8 P10.5 P10.4 / EPA16 P10.3 / SD1 P10.2 / SC1 / CHS# P10.1 / SD0 P10.0 / SC0 P11.4 / PWM4 P11.5 / PWM5 P11.6 / PWM6 P11.7 / PWM7 P11.3 / PWM3 P11.2 / PWM2 P11.1 / PWM1 P11.0 / PWM0 VSS VCC P12.4 P12.0 P12.1 P12.2 P12.3 VSS NC VCC NC RESET# NMI VREF ANGND ACH0 ACH1 ACH2 ACH3 ACH4 ACH5
This pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable. This pin supplies voltage to the code RAM. Maintain at 5 volts to retain data in code RAM. NC pins must be unconnected to prevent accidental entry into a test mode.
A4461-02
Preliminary Datasheet
NC NC NC NC EA# VCC PLLEN XTAL2 XTAL1 VSS VCC P2.7 / CLKOUT P2.6 / ONCE# P2.5 P2.4 /RXD1 P2.3 / TXD1 P2.2 / EXTINT P2.1 / RXD0 P2.0 / TXD0 VCC VSS CRBUSY# CROUT CRIN CRDCLK VCC NC VSS VSS ACH15 ACH14 ACH13 ACH12 ACH11 ACH10 ACH9 ACH8 ACH7 ACH6 NC
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
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80C196EA - Commercial
Table 2. 80C196EA 160-pin QFP Package Pin Assignments
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name AD0 / P3.0 AD1 / P3.1 AD2 / P3.2 AD3 / P3.3 AD4 / P3.4 AD5 / P3.5 AD6 / P3.6 AD7 / P3.7 VCC VCC VSS VSS AD8 / P4.0 AD9 / P4.1 AD10 / P4.2 AD11 / P4.3 AD12 / P4.4 AD13 / P4.5 AD14 / P4.6 AD15 / P4.7 P5.7 / RPD P5.4/BREQ#/TMODE# P5.6 / READY P5.1 / INST P5.0 / ALE P5.5 / BHE# / WRH# P5.3 / RD# P5.2 / WR# / WRL# VSS VCC A20 / EPORT.4 A16 / EPORT.0 A17 / EPORT.1 A18 / EPORT.2 A19 / EPORT.3 EPORT.5 / CS0# EPORT.6 / CS1# EPORT.7 / CS2# NC NC Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 NC NC NC NC EA# VCC PLLEN XTAL2 XTAL1 VSS VCC P2.7 / CLKOUT P2.6 / ONCE# P2.5 P2.4 / RXD1 P2.3 / TXD1 P2.2 / EXTINT P2.1 / RXD0 P2.0 / TXD0 VCC VSS CRBUSY# CROUT CRIN CRDCLK VCC NC VSS VSS ACH15 ACH14 ACH13 ACH12 ACH11 ACH10 ACH9 ACH8 ACH7 ACH6 NC Name Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name ACH5 ACH4 ACH3 ACH2 ACH1 ACH0 ANGND VREF NMI RESET# NC VCC NC VSS P12.3 P12.2 P12.1 P12.0 P12.4 VCC VSS P11.0 / PWM0 P11.1 / PWM1 P11.2 / PWM2 P11.3 / PWM3 P11.7 / PWM7 P11.6 / PWM6 P11.5 / PWM5 P11.4 / PWM4 P10.0 / SC0 P10.1 / SD0 P10.2 / SC1 P10.3 / SD1 P10.4 / EPA16 P10.5 P8.0 / EPA8 P8.1 / EPA9 P8.2 / EPA10 P8.3 / EPA11 P8.4 /EPA12 Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 NC P8.5 / EPA13 P8.6 / EPA14 P8.7 / EPA15 P7.7 / EPA7 / T4RST P7.6 / EPA6 / T4CLK VCC VSS P7.5 / EPA5 / T3RST P7.4 / EPA4 / T3CLK P7.3 / EPA3 / T2RST P7.2 / EPA2 / T2CLK P7.1 / EPA1 / T1RST P7.0 / EPA0 / T1CLK P9.0 / OS0 P9.1 / OS1 P9.2 / OS2 P9.3 / OS3 P9.4 / OS4 P9.5 / OS5 P9.6 / OS6 P9.7 / OS7 A0 A1 A2 A3 A4 A5 A6 A7 VSS VCC A8 A9 A10 A11 A12 A13 A14 A15 Name
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Preliminary Datasheet
80C196EA - Commercial
Table 3. Pin Assignment Arranged by Functional Categories (Sheet 1 of 2)
Addr & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Pin 143 144 145 146 147 148 149 150 153 154 155 156 157 158 159 160 32 33 34 35 31 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 Input/Output Name P2.0 / TXD0 P2.1 / RXD0 P2.2 P2.3 / TXD1 P2.4 / RXD1 P2.5 P2.6 P2.7 P3.0 P3.1 R3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 EPORT.0 EPORT.1 EPORT.2 EPORT.3 EPORT.4 EPORT.5 EPORT.6 Pin 59 58 57 56 55 54 53 52 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 25 24 28 27 22 26 23 21 32 33 34 35 31 36 37 Input/Output (Cont'd) Name EPORT.7 P7.0 / EPA0 / T1CLK P7.1 / EPA1 / T1RST P7.2 / EPA2 / T2CLK P7.3 / EPA3 / T2RST P7.4 / EPA4 / T3CLK P7.5 / EPA5 / T3RST P7.6 / EPA6 / T4CLK P7.7 / EPA7 / T4RST P8.0 / EPA8 P8.1 / EPA9 P8.2 / EPA10 P8.3 / EPA11 P8.4 / EPA12 P8.5 / EPA13 P8.6 / EPA14 P8.7 / EPA15 P9.0 / OS0 P9.1 / OS1 P9.2 / OS2 P9.3 / OS3 P9.4 / OS4 P9.5 / OS5 P9.6 / OS6 P9.7 / OS7 P10.0 / SC0 P10.1 / SD0 P10.2 / SC1 P10.3 / SD1 P10.4 / EPA16 P10.5 P11.0 / PWM0 P11.1 / PWM1 P11.2 / PWM2 P11.3 / PWM3 P11.4 / PWM4 P11.5 / PWM5 P11.6 / PWM6 P11.7 / PWM7 Pin 38 134 133 132 131 130 129 126 125 116 117 118 119 120 122 123 124 135 136 137 138 139 140 141 142 110 111 112 113 114 115 102 103 104 105 109 108 107 106 WR#/WRL# 28 ALE BHE#/WRH# BREQ# CS0# CS1# CS2# INST RD# READY Bus Control & Status Name Pin 25 26 22 36 37 38 24 27 23 ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 ACH8 ACH9 ACH10 ACH11 ACH12 ACH13 ACH14 ACH15 Analog Inputs Name Pin 86 85 84 83 82 81 79 78 77 76 75 74 73 72 71 70 P12.0 P12.1 P12.2 P12.3 P12.4 Input/Output (Cont'd) Name Pin 98 97 96 95 99
Preliminary Datasheet
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80C196EA - Commercial
Table 3. Pin Assignment Arranged by Functional Categories (Sheet 2 of 2)
Power & Ground Name ANGND VCC VSS V REF 87 9, 10, 30, 46 , 51, 60, 66, 92, 100, 127, 152 11, 12, 29, 50, 61, 68, 69, 94, 101, 128, 151 88 Pins Processor Control Name CLKOUT EA# EXTINT NMI ONCE# No Connection Name NC Pins 39-44, 67, 69, 80, 91, 93, 121 PLLEN RESET# RPD TMODE# XTAL1 XTAL2 Pin 52 45 57 89 53 47 90 21 22 49 48
This pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable. This pin supplies voltage to code RAM. To retain data, maintain 5 volts. Always leave NC (no connect) pins unconnected to prevent accidental entry into test modes.
Code Debug Name CRBUSY# CRDCLK CRIN CROUT Pin 62 65 64 63
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Preliminary Datasheet
80C196EA - Commercial
4.0
Signals
Table 4. Signal Descriptions (Sheet 1 of 3)
Name Type Address Latch Enable ALE O This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. An external latch can use this signal to demultiplex address from the address/data bus. Byte High Enable During 16-bit bus cycles, this active-low output signal is asserted for word and high-byte reads and writes to external memory. BHE# indicates that valid data is being transferred over the upper half of the system data bus. Use BHE#, in conjunction with A0, to determine which memory byte is being transferred over the system bus: BHE# O BHE# 0 0 1 A0 0 1 0 Byte(s) Accessed both bytes high byte only low byte only Description
BHE# shares a package pin with WRH#. The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#. Clock Output CLKOUT O Output of the internal clock generator. CLKOUT has a 50% duty cycle. shares a package pin External Interrupt In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation. The interrupt need not be enabled, but the pin must be configured as a special-function input. If the EXTINT interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. Instruction Fetch INST O This active-high output signal is valid only during external memory bus cycles. When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. INST is low for data accesses, including interrupt vector fetches and chip configuration byte reads. INST is low during internal memory fetches. Nonmaskable Interrupt NMI I In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than one state time to guarantee that it is recognized. On-circuit Emulation Holding ONCE during the rising edge of RESET# places the device into on-circuit emulation (ONCE) mode. PLLEN must also be held low. This mode puts all pins into a high-impedance state, thereby isolating the device from other components in the system. The value of ONCE is latched when the RESET# pin goes inactive. While the device is in ONCE mode, you can debug the system using a clip-on emulator. To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent inadvertent entry into ONCE mode, .
EXTINT
I
ONCE
I
Preliminary Datasheet
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80C196EA - Commercial
Table 4. Signal Descriptions (Sheet 2 of 3)
Name Type Read RD# O Read-signal output to external memory. RD# is asserted only during external memory reads. Ready Input This active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally. When READY is high, CPU operation continues in a normal manner with wait states inserted as programmed in the chip configuration registers . READY is ignored for all internal memory accesses. Reset A level-sensitive reset input to and open-drain system reset output from the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown and idle modes, asserting RESET# causes the chip to reset and return to normal operating mode. After a device reset, the first instruction fetch is from FF2080H. Receive Serial Data RXD I/O In modes 1, 2, and 3, RXD receive serial port input data. In mode 0, functions as either input or open-drain output for data. Description
READY
I
RESET#
I/O
Test-Mode Entry If this pin is held low during reset, the device will enter a test mode. The value of several other pins defines the actual test mode. All test modes, except test-ROM execution, are reserved for Intel factory use. If you choose to configure this signal as an input, always hold it high during reset and ensure that your system meets the VIH specification to prevent inadvertent entry into test mode. TMODE# with P5.4 and BREQ#. Transmit Serial Data TXD O In serial I/O modes 1, 2, and 3, TXD transmit serial port output data. In mode 0, the serial clock output. TXD with . VCC PWR Digital Supply Voltage Connect each VCC pin to the digital supply voltage. Digital Circuit Ground V SS GND These pins supply ground for the digital circuitry. Connect each VSS pin to ground through the lowest possible impedance path. Write WR# O This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# is multiplexed with . The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Write High During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. WRH# with BHE#. The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
TMODE#
I
WRH#
O
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Preliminary Datasheet
80C196EA - Commercial
Table 4. Signal Descriptions (Sheet 3 of 3)
Name Type Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# with WR#. The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Input Crystal/Resonator or External Clock Input XTAL1 I Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1. Inverted Output for the Crystal/Resonator XTAL2 O Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator. Description
WRL#
O
Preliminary Datasheet
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80C196EA - Commercial
5.0
Address Map
Table 5. 80C196EA Address Map
Hex Address FFFFFF FF4000 FF3FFF FF2140 FF213F FF20C0 FF20BF FF2080 FF207F FF2000 FF1FFF FF1000 FF0FFF FF0400 FF03FF FF0000 FEFFFF 1F0000 1EFFFF 002000 001FFF 001FE0 001FDF 001C00 001BFF 001000 000FFF 000400 0003FF 000100 0000FF 00001A 000019 000000 Description (Note 1, Note 2) External device (memory or I/O) connected to address/data bus Program memory Special-purpose memory (PIH vectors) Program memory (After reset, the first instruction is fetched from FF2080H.) Special-purpose memory (CCBs, interrupt vectors, PTS vectors) External device (memory or I/O) connected to address/data bus Internal code/data RAM (identically mapped from page 00H) Reserved for in-circuit emulators Overlaid memory (reserved for future devices); locations xF0000-xF03FFH are reserved for in-circuit emulators External device (memory or I/O) connected to address/data bus Memory-mapped special-function registers (SFRs) Addressing Modes Indirect, indexed, extended Indirect, indexed, extended (3) Indirect, indexed, extended (3) Indirect, indexed, extended (3) Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended -- Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended, windowed direct Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, windowed direct Direct, indirect, indexed Direct, indirect, indexed
Peripheral special-function registers (SFRs)
External device (memory or I/O) connected to address/data bus Internal code/data RAM (identically mapped into page FFH) Upper register file (general-purpose register RAM) Lower register file (general-purpose register RAM) Lower register file (stack pointer and CPU SFRs)
NOTES: 1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits. 2. The contents or functions of reserved locations may change in future device revisions, in which case a program that relies on one or more of these locations might not function properly. 3. External memory occupies the boot memory partition, FF2080-FF3FFFH.
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Preliminary Datasheet
80C196EA - Commercial
6.0
Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ................................... -60C to +150C Supply Voltage with Respect to VSS ............... -0.5 V to +7.0 V Power Dissipation ........................................................... 1.5 W
NOTICE: This document contains information on products in the design phase of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias)................ 0C to +70C VCC (Digital Supply Voltage) .............................. 4.5 V to 5.5 V VREF (Analog Supply Voltage) ........................... 4.5 V to 5.5 V FXTAL1 (Input frequency for VCC = 4.5 V - 5.5 V) (Note 1)................................................ 20 MHz to 40 MHz
NOTE: 1. This device is static and should operate below 1 Hz, but has been tested only down to 20 MHz.
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
6.1
DC Characteristics
Table 6. DC Characteristics at VCC = 4.5 V - 5.5 V (Sheet 1 of 2)
Sym Parameter Min Typ (1) Max Units Test Conditions XTAL1 = 40 MHz VCC = 5.5 V Device in Reset XTAL1 = 40 MHz VCC = 5.5 V VCC = 5.5 V XTAL1 = 40 MHz VCC = VREF= 5.5 V Device in Reset VCC=5.5 V (4)
ICC IIDLE IPD IREF ICRVCC IINJD ILI ILI1 IIH VIL1 VIH1 VIL2
VCC supply current Idle mode current Powerdown mode current A/D reference supply current Code RAM VCC Supply Current Maximum injection current per port on bidirectional pins Input leakage current (Standard inputs except analog inputs) Input leakage current (analog inputs) Input high current (NMI only) Input low voltage Input high voltage Input low voltage -0.5 0.7 VCC -0.5 -10
120
135
mA
60 50
95
mA A
5 110 10
mA A mA
-10
10
A
VSS < VIN < VCC VSS + 100 mV < VIN < VREF - 100 mV NMI = VCC = 5.5 V (2) (2) (3)
-300
300 175 0.3 VCC VCC + 0.5 0.4 VCC
nA A V V V
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For P2.7:0, P3.7:0, P4.7:0, P5.7:0, P6.7:0, P10.3:0, P11.7:0, P12.4:0, AD15:0, EA#, RESET#, PLLEN, NMI, TDI, TCLK, ONCE#, and XTAL1. 3. For P7.7:0, P8.7:0, P9.7:0, and P10.5:4. 4. The maximum injection current is not tested. The device is designed to meet this specification. 5. Pin capacitance is not tested. This value is based on design simulations.
Preliminary Datasheet
11
80C196EA - Commercial
Table 6. DC Characteristics at VCC = 4.5 V - 5.5 V (Sheet 2 of 2)
Sym V IH2 V OL1 Parameter Input high voltage Output low voltage (output configured as complementary) Output high voltage (output configured as complementary) Output low voltage in reset Output high current in reset -30 -65 -75 -5 -8 -10 VCC - 1 700 10 9 95 VCC - 0.3 VCC - 0.7 VCC - 1.5 0.5 -120 -240 -280 -50 -110 -130 Min 0.7 VCC Typ (1) Max VCC + 0.5 0.3 0.45 1.5 Units V V (3) IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA IOL = 15 A V OH2 = VCC - 1 V V OH2 = VCC - 2.5 V V OH2 = VCC - 4 V V OH3 = VCC - 1 V V OH3 = VCC - 2.5 V V OH3 = VCC - 4 V IOH = -15 A Test Conditions
VOH1 VOL2 IOH2
V V A
IOH3 VOH2 VHYS CS RRST
Output high current in reset on Port 11 Output high voltage in reset Hysteresis voltage on all inputs except XTAL1 Pin Capacitance (any pin to VSS) Pull-up resistor on RESET# pin
A V mV pF k
(5) V CC = 5.5 V, V IN = 4.0 V
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For P2.7:0, P3.7:0, P4.7:0, P5.7:0, P6.7:0, P10.3:0, P11.7:0, P12.4:0, AD15:0, EA#, RESET#, PLLEN, NMI, TDI, TCLK, ONCE#, and XTAL1. 3. For P7.7:0, P8.7:0, P9.7:0, and P10.5:4. 4. The maximum injection current is not tested. The device is designed to meet this specification. 5. Pin capacitance is not tested. This value is based on design simulations.
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Preliminary Datasheet
80C196EA - Commercial
6.2
AC Characteristics -- Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 1 of 2)
Symbol FXTAL1 Parameter Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Operating frequency, f = FXTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode t TAVDV TRLDV TCHDV TRHDZ TRXDX TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TQVWH TCHWH TWLWH Period, t = 1/f Address Valid to Input Data Valid RD# Low to Input Data Valid CLKOUT High to Input Data valid RD# High to Input Data Float Data Hold after RD# Inactive XTAL1 Rising Edge to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling to ALE Rising ALE Falling to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Low Address Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT Low RD# Low to RD# High RD# High to ALE Rising RD# Low to Address Float ALE Low to WR# Low Data Stable to WR# Rising Edge CLKOUT High to WR# Rising Edge WR# Low to WR# High t - 12 t - 14 - 10 t - 10 10 t - 10 t - 15 t - 15 t - 15 - 10 t - 12 t-5 t + 15 5 10 t - 10 - 10 - 10 4t t + 10 0 3 2t t + 10 10 10 50 25 50 3t - 40 t - 18 2t - 35 t+5 ns ns (2) ns (2) ns (9) ns ns ns (9) ns (9) ns (9) ns (9) ns (9) ns (2) ns ns ns ns ns (9) ns (2) ns (3) ns ns Min 20 10 20 Max 40 20 40 Units MHz (1, 8) MHz (8) MHz (8)
f
ns (2)
ns (9) ns (2)
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. If wait states are used, add 2t x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. When forcing wait states using the BUSCON register, add 2t x n. 5. Exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 8. Device is static by design but has been tested only down to 20 MHz. 9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
Preliminary Datasheet
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80C196EA - Commercial
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 2 of 2)
Symbol TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX TWHSH TRHSH TAVYV TCLYX TYLYH Parameter Data Hold after WR# High WR# High to ALE High BHE#, INST Hold after WR# High AD15:8, CSx# Hold after WR# High BHE#, INST Hold after RD# High AD15:8, CSx# Hold after RD# High A20:0, CSx# Hold after WR# High A20:0, CSx# Hold after RD# High AD15:0 Valid to READY Setup READY Hold after CLKOUT Low Non-READY Time 0 Min t - 20 t - 15 t-4 t-4 t-5 t-5 0 0 2t - 40 2t - 40 t + 10 Max Units ns ns ns ns (6) ns ns (6) ns ns ns (4) ns (5, 7, 9) ns
No Upper Limit
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. If wait states are used, add 2t x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. When forcing wait states using the BUSCON register, add 2t x n. 5. Exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 8. Device is static by design but has been tested only down to 20 MHz. 9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
Table 8. AC Timing Symbol Definitions
Signals A B C D
Conditions W X Y WR#, WRH#, WRL# XTAL1 READY H L V X Z High Low Valid No Longer Valid Floating
Address BHE# CLKOUT Input Data
L Q R S
ALE Output Data RD# CSx#
Address bus (demultiplexed mode) or address/data bus (multiplexed mode)
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Preliminary Datasheet
80C196EA - Commercial
Figure 4. System Bus Timing Diagram (Multiplexed Bus Mode)
TCLCL t TCLLH TCHDV TRLCL TCHCL
CLKOUT
TLLCH TLHLH TLLRL TRHLH TLHLL
ALE
TRLRH TRLAZ TRHDZ
RD#
TAVLL TRLDV TLLAX TAVDV Data In TLLWL TWLWH TCHWH TWHLH TWHQX
AD15:0 (read)
Address Out
WR#
TQVWH
AD15:0 (write) BHE#, INST
Address Out
Data Out
Address Out TWHBX, TRHBX
TWHAX, TRHAX
AD15:8 A20:16 CSx#
High Address Out
Extended Address Out TWHSH, TRHSH
A3252-01
Preliminary Datasheet
15
80C196EA - Commercial
Figure 5. READY Timing Diagram (Multiplexed Bus Mode)
TCLYX (max)
CLKOUT
TAVYV TCLYX (min)
READY
TLHLH + 2t
ALE
TRLRH + 2t
RD# AD15:0 (read) WR#
TRLDV + 2t TAVDV + 2t Address Out TWLWH + 2t Data In
TQVWH + 2t
AD15:0 (write) BHE#, INST A20:16 CSx#
Address Out
Data Out
Extended Address Out
A3249-01
16
Preliminary Datasheet
80C196EA - Commercial
6.3
AC Characteristics -- Demultiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 9. AC Characteristics, Demultiplexed Bus Mode
Symbol FXTAL1 f t TAVDV TRLDV TAVWL TAVRL TSLDV TCHDV TRHDZ TRHRL TRXDX TXHCH TCLCL TCHCL TCLLH TRLCL TRLRH TRHLH TWLCL TQVWH TCHWH TWLWH TWHQX TWHBX TWHAX TRHBX TRHAX TAVYV TCLYX TYLYH Parameter Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Operating frequency, f = FXTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode Period, t = 1/f Address Valid to Input Data Valid RD# Low to Input Data Valid Address Valid to WR# Low Address Valid to RD# Low Chip Select Low to Data Valid CLKOUT Rising Edge to Input Data Valid RD# High to Input Data Float Read High to Next Read Low Data Hold after RD# Inactive XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling ALE Rising RD# Low to CLKOUT Low RD# Low to RD# High RD# Rising to ALE Rising WR# Low to CLKOUT Falling Data Stable to WR# Rising Edge CLKOUT High to WR# Rising Edge WR# Low to WR# High Data Hold after WR# Rising Edge BHE#, INST Hold after WR# High A20:0, CSx# Hold after WR# High BHE#, INST Hold after RD# High A20:0, CSx# Hold after RD# High A20:0 Valid to READY Setup READY Hold after CLKOUT Low Non READY Time 0 t-5 0 10 2t t - 10 - 10 -5 3t - 12 t-4 - 12 3t - 18 -5 3t - 15 t t 0 t 0 3t - 25 2t - 28 No Upper Limit t + 15 10 t + 12 5 t + 10 10 5 35 t t-8 4t - 27 2t - 25 t-5 Min 20 10 20 25 Max 40 20 40 50 4t - 23 3t - 25 Units MHz (1,8) MHz (8) Mhz ns ns (2) ns (2) ns ns ns (2) ns (9) ns ns ns ns (9) ns (9) ns (9) ns (9) ns (9) ns (2)
ns (3)
ns (9) ns (3) ns (9) ns (2) ns ns ns ns ns ns (4) ns (5, 7,9) ns
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. If wait states are used, add 2t x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. When forcing wait states using the BUSCON register, add 2t x n. 5. Exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 8. Device is static by design but has been tested only down to 20 MHz. 9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
Preliminary Datasheet
17
80C196EA - Commercial
Figure 6. System Bus Timing Diagram (Demultiplexed Bus Mode)
TCHCL TCLLH TCLCL t TCHWH
CLKOUT
TRHLH
ALE
TRHRL TRHDZ TRHAX
TAVRL
TRLRH TCHDV TRLDV TAVDV TSLDV Data In TWLCL
RD#
AD15:0 (read)
TAVWL
TWHQX TWHAX TWLWH
WR#
TQVWH
AD15:0 (write) BHE#, INST A20:0 CSx#
Address Out
Data Out TWHBX, TRHBX
A5397-01
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Preliminary Datasheet
80C196EA - Commercial
Figure 7. READY Timing Diagram (Demultiplexed Bus Mode)
TCHYX (max)
CLKOUT
TAVYV TCHYX (min)
READY
TLHLH + 2t
ALE
TRLRH + 2t
RD#
TRLDV + 2t
AD15:0 (read) WR#
TAVDV + 2t Data In TWLWH + 2t
TQVWH + 2t
AD15:0 (write) BHE#, INST A20:16 CSx#
Data Out
Extended Address Out
A5398-01
Preliminary Datasheet
19
80C196EA - Commercial
6.4
Deferred Bus Timing Mode
Deferred Bus Cycle Mode: This bus mode (enabled by setting CCB1.5) reduces bus contention when using the 80C196EA in demultiplexed mode with slow memories. As shown in Figure 8, a delay of 2t occurs in the first bus cycle following a chip-select output change and the first write cycle following a read cycle.
Figure 8. Deferred Bus Mode Timing Diagram
CLKOUT
TLHLH + 2t TWHLH + 2t
ALE
TRHLH + 2t TAVRL + 2t
RD#
TAVDV+ 2t
AD15:0 (read) WR# AD15:0 (write) BHE#, INST A20:0 CSx#
Data In TAVWL + 2t
Data In
Data Out
Data Out
Data Out
Address Out
Valid
Valid
A3246-02
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Preliminary Datasheet
80C196EA - Commercial
6.5
AC Characteristics -- Serial Port, Shift Register Mode
Table 10. Serial Port Timing -- Shift Register Mode
Symbol Parameter Serial Port Clock period TXLXL SP_BAUD x002H SP_BAUD = x001H1 Serial Port Clock falling edge to rising edge TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ SP_BAUD x002H SP_BAUD = x001H1 Output data setup to clock high Output data hold after clock high Next output data valid after clock high Input data setup to clock high Input data hold after clock high Last clock high to output float 2t + 30 0 t + 30 4t - 27 2t - 27 4t - 30 2t - 30 2t + 30 4t + 27 2t + 27 ns ns ns ns ns ns ns ns 6t 4t ns ns Min Max Units
1. The minimum baud-rate (SP_BAUD) register value for receive is x002H and the minimum baud-rate (SP_BAUD) register value for transmit is x001H.
Figure 9. Serial Port Waveform -- Shift Register Mode
TXLXL TXDx TQVXH RXDx (Out) RXDx (In)
0 1 2
TXLXH
3
TXHQV
4
TXHQX
5 6
TXHQZ
7
TDVXH
Valid Valid Valid
TXHDX
Valid Valid Valid Valid Valid
A2080-03
Preliminary Datasheet
21
80C196EA - Commercial
6.6
AC Characteristics -- Synchronous Serial Port
Table 11. Synchronous Serial Port Timing
Symbol TCLCL TCLCH TD1DV TCXDV TCXDX TDVCX TDXCX Parameter Synchronous Serial Port Clock period Synchronous Serial Port Clock falling edge to rising edge Setup time for MSB output Setup time for D6:0 output Output data hold after clock low Setup time for input data Input data hold after clock high t 10 t+5 Min 8t 4t 2t 3t + 20 3t + 20 Max Units ns ns ns ns ns ns ns
Figure 10. Synchronous Serial Port
SCx (normal transfers)
1
2
3
4
5
6
7
8
TCLCH TCLCL
STE Bit
SDx (out)
MSB
D6
D5
D4
D3
D2
D1
D0
TD1DV
SDx (in)
valid valid valid valid valid valid valid valid
TDVCX
SCx (handshaking transfers) 1 2 3 4 5 6 7
TDXCX
8
TCXDX
TCXDV
Slave Receiver Pulls SCx low
A4512-01
22
Preliminary Datasheet
80C196EA - Commercial
6.7
A/D Sample and Conversion Times
Two parameters, sample time and conversion time, control the time required for an A/D conversion. The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. If this time is too short, the sample capacitor will not charge completely. If the sample time is too long, the input voltage may change and cause conversion errors. The conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. The conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. Excessively long conversion times allow the sample capacitor to discharge, degrading accuracy. The AD_TIME register programs the A/D sample and conversion times. Use the TSAM and TCONV specifications in Table 12 and Table 14 to determine appropriate values for SAM and CONV; otherwise, erroneous conversion results may occur. When the SAM and CONV values are known, write them to the AD_TIME register. Do not write to this register while a conversion is in progress; the results are unpredictable. Use the following formulas to determine the SAM and CONV values.
T xf-2 SAM SAM = -----------------------------8 T xf-3 CONV CONV = ---------------------------------- - 1 2xB
where:
SAM CONV TSAM TCONV f B equals a number, 1 to 7 equals a number, 2 to 31 is the sample time, in sec (Table 12 and Table 14) is the conversion time, in sec (Table 12 and Table 14) is the operating frequency, in MHz is the number of bits to be converted (8 or 10)
At 40 Mhz, to meet TSAM and TCONV minimum specifications:
10-bit mode:
SAM = [ 5, 6, 7 ] T SAM 1s CONV = [ 18, 19, 20, ..., 31 ] T CONV 10s SAM = [ 5, 6, 7 ] T SAM 1s CONV = [ 23, 24, ..., 31 ] T CONV 10s
8-bit mode:
Preliminary Datasheet
23
80C196EA - Commercial
6.7.1
AC Characteristics -- A/D Converter, 10-bit Mode
Table 12. 10-bit A/D Operating Conditions (1)
Symbol TA V CC VREF TSAM TCONV Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Min 0 4.50 4.50 1.0 10.0 15.0 Max 70 5.50 5.50 Units C V V s s (2) (3) (3) Notes
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. V REF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 13. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (7)
Parameter Resolution Absolute Error Full-scale Error Zero Offset Error Nonlinearity Differential Nonlinearity Channel-to-channel Matching Repeatability Temperature Coefficients: Offset Full-scale Differential Nonlinearity Off-isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage 3.0 100 - 300 300 - 60 - 60 750 ANGND 1.2K VREF W V pF nA (8) 0.009 0.009 0.009 - 60 dB LSB/C (2,3,4) (2,3) (2,3) (5) (6) 0.1 0.25 0.25 0.5 0.25 0.5 1.0 2.0 - 0.75 0 0 3.0 + 0.75 1.0 LSBs Typical (2) Min 1024 10 0 Max 1024 10 3.0 Units (1) Levels Bits Notes
NOTES: 1. An LSB, as used here, has a value of approximately 5 mV. 2. Most parts will meet these values at 25C, but they are not tested or guaranteed. 3. DC to 100 KHz. 4. Multiplexer break-before-make guaranteed. 5. Resistance from device pin, through internal multiplexer, to sample capacitor. 6. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions were performed with processor in idle mode. 8. 100 mV < VIN < VREF - 100 mV.
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Preliminary Datasheet
80C196EA - Commercial
6.7.2
AC Characteristics -- A/D Converter, 8-bit Mode
Table 14. 8-bit A/D Operating Conditions (1)
Symbol TA VCC VREF TSAM TCONV Description Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Min 0 4.50 4.50 1.0 8.0 15.0 Max 70 5.50 5.50 Units Notes
C
V V s s (2) (3) (3)
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 15. 8-bit Mode A/D Characteristics Over Specified Operating Conditions (7)
Parameter Resolution Absolute Error Full-scale Error Zero Offset Error Nonlinearity Differential Nonlinearity Channel-to-channel Matching Repeatability Temperature Coefficients: Offset Full-scale Differential Nonlinearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage 3.0 100 - 300 300 - 60 - 60 750 ANGND 1.2K VREF V pF nA (8) 0.003 LSB/C 0.25
0.5
Typical (2)
Min 256 8 0
Max 256 8 1.0
Units (1) Levels Bits
Notes
0.5 0 - 0.5 0 0 1.0 + 0.5 1.0 LSBs
- 60 dB
(2,3,4) (2,3) (2,3) (5) (6)
NOTES: 1. An LSB, as used here, has a value of approximately 20 mV. 2. Most parts will need these values at 25C, but they are not tested or guaranteed. 3. DC to 100 KHz. 4. Multiplexer break-before-make guaranteed. 5. Resistance from device pin, through internal multiplexer, to sample capacitor. 6. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions were performed with processor in idle mode. 8. 100 mV < V IN < VREF - 100 mV.
Preliminary Datasheet
25
80C196EA - Commercial
6.8
External Clock Drive
Table 16. External Clock Drive
Symbol 1/TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency (FXTAL1) Oscillator Period (TXTAL1) High Time Low Time Rise Time Fall Time Min 10 25 0.35TXTAL1 0.35TXTAL1 Max 40 (1) 100 0.65TXTAL1 0.65TXTAL1 10 10 Units MHz (2) ns ns ns ns ns
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. These values represent PLL-bypass mode.
Figure 11. External Clock Drive Waveforms
TXHXX 0.7 VCC + 0.5 V XTAL1
TXLXH TXLXX 0.3 VCC - 0.5 V 0.7 VCC + 0.5 V 0.3 VCC - 0.5 V TXLXL
TXHXL
A2119-03
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Preliminary Datasheet
80C196EA - Commercial
6.9
Test Output Waveforms
Figure 12. AC Testing Output Waveforms
3.5 V
2.0 V Test Points 0.8 V
2.0 V 0.8 V
0.45 V
Note: AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0".
A2120-04
Figure 13. Float Waveforms During 5.0 Volt Testing
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
Note: For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A2121-03
Preliminary Datasheet
27
80C196EA - Commercial
7.0
Thermal Characteristics
All thermal impedance data is approximate for static air conditions at 1 W of power dissipation. Values change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information.
Table 17. Thermal Characteristics
Package Type 160-pin QFP JA 34C/W JC 5C/W
7.1
80C196EA Errata
The 80C196EA may contain design defects or errors known as errata. Characterized errata that may cause the 80C196EA's behavior to deviate from published specifications are documented in a specification update. Specification updates can be obtained from your local Intel sales office or from the World Wide Web (www.intel.com).
8.0
DataSheet Revision History
This is the -001 version of the "80C196EA - Commercial" datasheet.
28
Preliminary Datasheet

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